The present invention relates to a comparator with a latch circuit and, more particularly, to a clock signal and an input data range of such a comparator.
A conventional comparator with a latch circuit has an arrangement as shown in FIG. 3. More specifically, in order to fetch data, a true clock signal .phi. is input to the base of a transistor 34 and a complementary clock signal .phi. is input to the base of a transistor 35. Since the transistors 34 and 35 constitute a differential pair, a current flowed through a transistor 36 constituting a constant current source is flowed through the transistor 34, and the transistor 35 is disabled. In this case, when input data IN input to the base of a transistor 30 constituting a differential pair with a transistor 31, which receives a reference voltage at the base, is higher than the reference voltage, the transistor 31 is disabled, and a current flowed through the transistor 34 is flowed through the transistor 30. A potential lowered by the current flowed through a resistor 28 from a potential Vcc appears at the collector of the transistor 30. More specifically, if a current flowed as a constant current is represented by I, the collector potential of the transistor 30 is given by Vcc-I.times.R.sub.28. On the other hand, the potential Vcc is applied to the collector of the transistor 31. When the input data is to be latched next, the complementary clock signal .phi. is input to the base of the transistor 34, and the true clock signal .phi. is input to the base of the transistor 35. The transistor 34 is disabled, and a current is flowed through the transistor 35. In this case, according to the previous state, a potential defined by Vcc-I.times.R.sub.28 as the collector potential of the transistor 30 is applied to the base of the transistor 32, and the potential Vcc as the collector potential of the transistor 31 is applied to the collector of the transistor 32. The potential Vcc as the collector potential of the transistor 31 is applied to the base of the transistor 33, and the potential Vcc-I.times.R.sub.28 as the collector potential of the transistor 30 is applied to the collector of the transistor 33. Therefore, since the transistors 30 and 31 constitute the differential pair, the transistor 32 is disabled, and a current is flowed through the transistor 33. Thus, the potential Vcc- I.times.R.sub.28 is applied to the collector of the transistor 30 common to that of the transistor 33, and the potential Vcc is applied to the collector of the transistor 31 common to that of the transistor 32. In other words, the previous state is latched.
In FIG. 3, reference numerals 30 to 36 denote NPN transistors; 28, 29, and 37, resistors; and 38, a power source.
In the conventional comparator with the latch circuit described above, since the transistor receiving the clock .phi. is located at the lowermost stage of a vertical structure, an input data range corresponds to a range of the power source Vcc to the clock input signal. For this reason, assume that an input data signal is driven by an amplifier and is input to the comparator with the latch circuit, and the amplifier and the latch circuit use a common power source. In this case, an output voltage of the amplifier is lower than the power source voltage. Therefore, the amplifier for driving the input data must have a power source of a higher potential than the power source voltage of the comparator with the latch circuit when the data signal input to the latch circuit has an amplitude up to the power source voltage. More specifically, the comparator with the latch circuit and the amplifier must have independent power sources.